Inversion of Vandermonde Matrices in FPGAs

In this thesis, we explore different algorithms for the inversion of Vandermonde matrices and the corresponding suitable architectures for implement in FPGA. The inversion of Vandermonde matrix is one of the three master projects of the topic, Implementation of a digital error correction algorithm for time-interleaved analog-to-digital converters. The project is divided into two major parts: algorithm comparison and optimization for inversion of Vandermonde matrix; architecture selection for implementation. A CORDIC algorithm for sine and cosine and Newton-Raphson based division are implemented as functional blocks. Acknowledgement First, we would like to especially thank to our supervisors Assistant Professor Oscar Gustafsson and Assistant Professor Per Löwenborg for giving the opportunity to do this thesis and giving us support and valuable guidance. We would like to thank to all members of the Electronics Systems group who help us and support our work. Last but not least, thanks to our family, Liu chen and Haiyan, for all the courage and support for our study here in Sweden. Table of contents Chapter 1 Overview.................................................................. 1 1.1 Purpose (background) .................................................. 1 1.1.